Spectral density waterfall plot of BLE trace
DSP pipeline of a polyphase channelizer with half-bin frequency offset correction.
Demodulated BLE signal.
Polyphase Channelizers with Frequency Offset - a Bluetooth LE Example
tomverbeure.github.io/2026/03/05/P...
Diagram of a single channel polyphase filter bank
Diagram of a multi-channel polyphase filter bank
Spectrum of a signal with multiple channels
Spectra of the individual channels at the exit of the channelizer
The Stunning Efficiency and Beauty of the Polyphase Channelizer
tomverbeure.github.io/2026/02/16/P...
I'm super excited to announce my latest project! 📢
🎸 Tuitar — A guitar training tool & DIY kit 🎛️
⚡ Runs in the terminal or standalone on ESP32.
🎵 Real-time tuning, fretboard tracking, signal analysis
🦀 Written in Rust & built with @ratatui.rs
⭐ GitHub: github.com/orhun/tuitar
#rustlang #ratatui
Ah, even more reasons to not get any work done 😁
I was featured in an article as an alumnus of @utwente.bsky.social
www.utwente.nl/en/stories/s...
Highly recommend it 👍
When ordering his book, I asked @johnromero.bsky.social if he could sign it on a random page. It took a while because I was busy, but I finally found it 😁 Awesome book!
The only downside is that I can't put it down once I start reading haha.
I was so happy when my best hand got like 250k chips. Then a friend showed me a casual 2.5 BILLION 🥲
OK, so I just recently discovered @babymetal.bsky.social and they are doing a concert here in the Netherlands May 13th. Guess where I'm going? 😁
Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you're stuck running at the speed of your dev board oscillator. This post outlines the frequency capabilities of the ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies.
Working on a new #FPGA blog post this evening. I'll be sharing the draft with my sponsors in the next few days. @yosyshq.com
"Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL, you're stuck running at the speed of your dev board oscillator..."
I'm going to start a regular stream about #opensource silicon. Topics will include design, verification, #fpga, openlane, formal, #tinytapeout, #ASIC bringup, chip validation.
If you're interested, please let me know what days / times work for you:
doodle.com/meeting/orga...
I recently added Beginning FPGA Graphics support for Radiona #ULX3S in addition to the @digilent.bsky.social Arty / Nexys Video, and iCEBreaker. Four years after it began, I continue to update this series to make #FPGA development accessible. 👷 projectf.io/posts/fpga-g...
I’m always looking for fun ways to show how chips work.
This interactive simulation actually lets you look inside a digital design as it’s running!
It’s a cellular automata by Alexander Mordvintsev and he taped out on Tiny Tapeout 9.
And no, it’s not a recording!
znah.net/tt09/
Man, am I glad I run Linux on all of my machines...
It's official, I'm going on vacation to Japan 🥳 Where do I go for vintage hardware (MSX, X68000, etc.)?
And other beautiful places too of course :D
We went from "Can it run Doom?" to "Can it run Quake?", and now to "Can it run Quake II?". The answer is "Yes" 😲
x.com/m_bitsnbites...
My Berserk manga collection is finally complete for now! Now I need another bookshelf in my lab for my technical books, because I don't have enough space for all my manga.
Made a lot of progress and here is the result with LED strips installed. Do not mind the unpacked boxes 😅
I have never done drugs, but I assume it feels like this, but is much cheaper...
store.steampowered.com/app/1349230/...
My dad painted clear lacquer on the table tops today. Tomorrow we're going to sand them and apply a second layer.
Mounted the table tops 😁
Oof, 2024 started terribly for Japan. My condolences to all who have and are still suffering.
Ah yeah, I just received my Dygma Defy!
Nearly finished the frame today and it is super strong! I also have the table tops, but now we have two days of Christmas and I don't want to bother the neighbors.
Made some progress today on my lab bench 😀
The very humble beginnings of my lab at home 😁 Trying out how to make the frame of the workbench.
This is a bit time sensitive, but... feel free to RT.
I'm looking for a bit of paid work (low to mid hundreds of USD) before year's end.
Most comfortable with embedded Rust and FPGA design using Amaranth HDL (and Python in general). I am willing to write C as well.
LET'S GOOOOOOOO!
https://twitter.com/MangaMoguraRE/status/1699012667267273181?s=20
