New Automotive Architectures Are Shaking Up Processor And Memory Choices
Exponential increases in data and a mix of performance requirements are driving a top-to-bottom rethinking of what works best where.
An explosion of data from sensors for assisted and autonomous driving, and the need to make real-time decisions based on that data, are placing unprecedented demands on memory and storage subsystems in vehicles.
semiengineering.com/new-automoti...
#automotive
05.03.2026 16:05
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Verifying Scale-Up And Scale-Out In Data Centers
Navigating a sea of standards and options in a rack and between racks. semiengineering.com/verifying-sc...
#DataCenters #ScaleUp #ScaleOut
04.03.2026 17:22
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Making Hybrid Bonding Better
Why this technology is so essential for multi-die assemblies, and how it can be improved.
The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipmakers are rethinking how devices are built, stacked, and powered.
semiengineering.com/making-hybri...
#semiconductor #hybridbonding
02.03.2026 16:39
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Wi-Fi 7 Moves To The IoT
What's behind the widespread adoption of extremely high-throughput wireless.
How Wi-Fi7 can manage different bands, how its capacity can be shared by multiple devices simultaneously, and how vendors are utilizing the standard’s different features.
semiengineering.com/wi-fi-7-move...
#IoT #WiFi7
01.03.2026 22:42
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Back-End Automation Tackles Growing Complexity:
As semiconductor packaging complexity rises, the industry faces gaps in data, inspection, and process integration.
semiengineering.com/back-end-aut...
#semiconductor
25.02.2026 16:30
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Changes In Chip Architectures At The Edge
YouTube video by Semiconductor Engineering
Changes In Chip Architectures At The Edge
How to build an efficient and flexible multi-die system for edge AI.
youtu.be/XK22FSKkyl0?...
#edgeAI #edgecomputing #npu #DSP #datacenters
24.02.2026 00:49
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Laser Arrays May Simplify Co-Packaged Optics
Monolithic tunable lasers can adapt statically and dynamically.
The move to co-packaged optics (CPO) holds the promise of putting photonic ICs and electronic ICs into the same package.
semiengineering.com/laser-arrays...
19.02.2026 16:01
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UCIe's Major Technical Components Are Now In Place
Version 3.0 of the interconnect standard doubles bandwidth and supports new use cases and enhanced manageability.
While UCIe was initially seen as feature-heavy, many of its management functions are optional, reducing adoption concerns and making the standard more flexible for developers.
semiengineering.com/ucies-major-...
#chiplets #UCIe
16.02.2026 21:23
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SemiEngineering's latest Low Power-High Performance newsletter
semiengineering.com/newsletter/l...
#NPUs #datacenters #GDDR7 #clockjitter
#MIPI #PCIe #semiconductor
11.02.2026 16:20
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Consumer, Med Tech Mushrooms As Quantum Closes In
Bio-inspired medical devices can gather more data than ever before, and HPC/quantum will massively speed up discovery rates; consumer self-testing will be slower.
Major developments are occurring in the bio-medical space, where new types of devices made of unusual materials & gels can measure tiny lab-grown brain cells, & sensors can measure every environmental & bodily function, from blood to heart & everything in between
semiengineering.com/bio-neuro-de...
09.02.2026 16:16
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Semiconductor Engineering's latest Test, Measurement and Analytics newsletter
semiengineering.com/newsletter/t...
#semiconductor
08.02.2026 16:38
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Why Move To 2nm?
Leading-edge chipmakers are starting to look at process node scaling very differently.
Power, performance, and area/cost are still the key metrics for chipmakers, yet how those metrics are weighted and implemented can vary significantly.
semiengineering.com/why-move-to-...
#2nm #semiconductor
04.02.2026 17:06
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Multi-Die Assemblies Require More Detailed Test Plan Earlier
Understanding connectivity issues and interactions are only part of the problem; ECOs can cause unexpected problems in other areas.
Multi-die assemblies are forcing engineering teams to map out how the various components will function and interact much earlier in the design process, and to develop a detailed plan for how they will be verified and tested. semiengineering.com/multi-die-as...
#semiconductor
03.02.2026 16:57
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