Jan Gray

The Reluctant Astronaut

TCM may fall to Ellison Skywatch but in the meantime they’re doing their bit programming films like this amazing doc.

See also Errol Morris’ The Unknown Known on so smug Donald Rumsfeld. Another infuriating one was the 2007 doc No End in Sight. Grrr.

“That’s much too vulgar a display of power” — possessed Regan MacNeil

No, I really really really really prefer classic Outlook. Really.

Yes, I would like to reconnect that fourth unimportant exchange server account without having to authenticate with Windows Hello.

Etc.

I helped build the damn company but it is nearing time to move elsewhere lock stock and barrel.

Microsoft and other software companies have embraced a pernicous habit of forcing unwanted features on their loyal users without so much as an opt-in or opt-out.

They behave as if their customers have no choice. At their peril.

It underscores how far behing FPGAs are falling on memory bandwidth, with end-of-lifed Virtex UltraScale+ HBM2 devices last year (0.4 TB/s), and perhaps the same fate looming for Versal Premium HBM2e devices (0.8 TB/s).

Will there be AMD Versal HBM3s? Will there be Versals w/ beaucoup LPDDR5X?

Cue @fclc :-)

A picture of PEW poll on global attitude survey, saying the % who rate the morality and ethics of people in their country as good vs bad, where the US has the worst rankings and Canada the best

Americans: we live in a fallen state—embroiled by sin, cheating, lying, and evil. You cannot trust anyone, not even those who claim to know you best

Canadians: I love my neighbors and my friends!

BTW this blockbuster will use at least 4+16*17 = 276 known good dice, in one package, for a max DRAM bandwidth of perhaps 16*4=64 TB/s.

At ~4 pJ/bit (??), that's 2000 W (??) just for the DRAM interface.

👇

Love it Bruno!

My PDP-11/45 doesn’t run yet but I do run 2.11BSD on my PDP-11/53+ made from a KDJ11.

bsky.app/profile/jang...

My AMD/Xilinx forums >> Vivado >> Implementation complaint: Why has LUT6_2 been removed from UG974 between 2024.2 and 2025.1? Between Vivado 2024.2 and 2025.1, it appears that LUT6_2 has been removed from UG974, the UltraScale+ Libraries Guide. See for yourself, search LUT6_2 with different release versions at https://docs.amd.com/r/2025.1-English/ug974-vivado-ultrascale-libraries/Introduction. With trepidation I reran a LUT6_2 design through Vivado 2025.2 and was relieved to find despite your documentation change, LUT6_2 is still a valid primitive, and still seems to be honored by Vivado 2025.2 My questions: Why is primitive now undocumented? Will it nevertheless be honored for the lifetime of Vivado targeting UltraScale+, or is AMD aiming to deprecate and remove it? LUT6_2 is the only way to explicitly force a particular and sometimes critical 5,5-LUT technology mapping in the Vivado implementation flow using RTL, short of adding hundreds of thousands of fine grained placement constraints. It also allows us to get a truer estimate of 6-LUT usage rather than lowering everything to 5-LUTs then (maybe) merging them in the mapper. For those of us that sometimes sweat every LUT, and floorplan, it is indispensible. Yes, we jealously covet control of that packing knob. You folks broke our LUT_MAP constraints and RLOC zipping. Please don't also break LUT6_2 5,5-LUT technology mapping. Thank you.

Sigh.

I just built a test circuit w/ Vivado 2025.2. Phew, it honors LUT6_2s, keeps two 5-LUTs packed.

Let us hope this is not a harbinger of intentions to remove LUT6_2 from UltraScale+ designers' toolboxes.

Alas, this seems to be another mistake that I must now waste time to try to disabuse AMD of. 🤦

Figure of the UltraScale+ LUT6_2 primitive, with outputs O6 and O5, instantiates a primitive 5,5-LUT, now ominously missing from the latest iterations of UG974.

When synthesis is clueless this can require instantiation of LUT6 and LUT6_2, see UG974.
docs.amd.com/r/en-US/ug97...
... ... ...

*** STOP PRESS! WTF! UG974 between 2024.2 and 2025.1 has deleted the LUT6_2 primitive. The WHOLE POINT of LUT6_2 is to enable explicit LUT-5,5s. ***

Where it matters:
1. Pick frequency and area constraints/budgets.
2. Manually map your datapath to 6-LUTs and 5,5-LUTs to hit them. May require rethinking the μarch.
3. Only then write and refine the RTL until the output matches the LUTs and delays you expect.
4. Go to 1.

"The Knowledge": 👇

Thank you. Yes my NoC routers datapaths are hand technology mapped and are FPGA optimal in area and delay.

The sand remembers
warm beaches and bright sunshine
this Rubin's damned hot!

Thank you!

The logic cluster's switchbox. Brings input signals in, sends output signals out to the rest of the device, and routes intra-cluster signals around. Fanout too.

The logic cluster's switchbox. Brings input signals in, sends output signals out to the rest of the device, and routes intra-cluster signals around. Fanout too.

Some rows and columns of programmable interconnect and some logic clusters hanging off them.

Another 256b-wide Hoplite router.

Logical layout of a neighborhood of a router. The yellow and blue signal cones represent control signals that are connected to hundreds of logic gates each. They converge on a rectangular site that is a 256b-wide Hoplite NoC router.

(From 2017) The Art of FPGA Design

A leucistic Douglas Squirrel, a visitor past, fondly remembered.

Happy Squirrel Appreciation Day from this leucistic Douglas Squirrel to you all.

Bravo and thank you.

The institutional buildings of 1960s Canada were extraordinarily well-built. Throwing them away would be madness.

The 1969 Science Centre is an incredible piece of architecture. It needs some work.

The new building complex is a kludge that will be inferior by any measure.

OSC’s sister, Munich’s vast and storied Deutsches Museum, faced serious river flooding and maintenance of a century. They decided to renew and reinvent in place, over years, preserving continuity of culture, buildings, access, institutions, and people. Despite the works it is a stunning experience.

A reminder of what we are losing to get this cheap shit metal and glass thing open.substack.com/pub/lloydalt...

Thank you very much, Lloyd, for your beautiful essay. I too loved that bridge, that brass, and especially the pandemonium of joy and discovery that was the Science Arcade, the wall of sound of gamelans and sine waves, a fraction of the 550 amazing exhibits where the course of my life was determined.

Photo of a young lady’s hair raising experience on a Van der Graaff generator boasting “wonders never cease”

Wonders ceased.

Some of the unforgettable ride down to the Valley Building. Especially nice on a school’s out snow day, with the birdsong and sometimes cardinals etc.

Me in my favorite place in the world — me and raw concrete in the great hall.

Photo of the shuttered bridge to the Tower Building, 2023. Harbinger of malign closures to come. Was I mad!

Photo of the sign announcing shuttered bridge to the Tower Building, 2023. Harbinger of malign closures to come. After closing this for one month everyone involved at Infrastructure Ontario and OSC leadership should have been fired.

Tuzo Wilson wept.

🧵