Rachit Nigam

Wooo! Congratulations Joe!!!

Very cool stuff! Thanks for the writeup!

Phew, survived the first grant submission and now onto prepping my first lecture! People weren't joking when they said you can't no-life as a prof. because you'll still have commitments tomorrow 😆

Building a "Rust for hardware design" requires the same so I spent the weekend writing a 2-page paper defining a criteria for "safe hardware description languages (HDLs)" and how they should complement, instead of competing with existing formal tools: people.csail.mit.edu/rachit/files...

A hopefully uncontroversial take is that Memory safety defines a class of *logical errors* that pointer-manipulating programs suffer from. By defining this category, we were able to create dynamic and static mechanisms to eliminate it.

People keep asking me what the "Rust for hardware design" would look like. Those who know their PL history know that, before we could build Rust, we had to define ideas like "Memory Safety".

Looks cool! Is it going to be streamed?

the Sloppy-Floppy-OS

I'm really excited to see where this line of work goes and what we can build with it! If you're around at ASPLOS and interested in this kind of work, come say hi and go watch the talks!!

Parameterized Hardware Design with Latency-Abstract Interfaces Hardware designs must use latency-insensitive (LI) interfaces when timing is input-dependent. When timing is input-independent, designs should use latency-sensitive (LS) interfaces for maximum perform...

1. Lilac (arxiv.org/abs/2401.02570) : Demonstrates how safe HDLs enable fundamentally new design abstractions!

2.Anvil (arxiv.org/abs/2503.19447): Explores how Filament's verification abstractions can be applied to a higher-level, message-passing HDL and enforce safety properties!

Our work on Filament (filamenthdl.com) defined a criteria for safe hardware description languages (HDLs) and showed that you can enforce it using a type system and introduce no overheads. This year's ASPLOS features two papers exploring safe HDLs:

Hardware design needs its own safe programming model but instead of memory, the problem is time! Every hardware module reasons about how time affects itself and everything it communicates with. Getting it wrong means bugs: reading meaningless values and using resources that are unavailable.

Hardware design should be SAFER!

Memory-safe software languages changed the world and allowed to us to build massively larger systems. At their heart, memory-safe languages eliminate a category of bugs that pointer-manipulating programs suffer from.

Folks showing up to ASPLOS: would there be interest in having a "junior faculty social"? I used to organize in-person socials for PhD students at PLDI (pltea.github.io) and think it would be fun to have an excuse to meet the cohort of junior faculty!

The SRC is awesome! Especially good for new junior faculty as a way to meet a wide set of soon-to-be-PhD applicants and learn about all the cool research they've been doing!

Interesting ref! Thank you!

Curious about some programming languages history: when/where did the idea of "Memory Safety" come from? Is there a good source that traces its development and formalization?

Continuing my long-running beef with "transpiler", I wrote a post trying to formalize different definitions of the word and why they don't work (for me): people.csail.mit.edu/rachit/post/...

(Not so secret goal: Get more people to read "On the Expressive Power of Programming Languages")

Q: Is it OK to get the references for my paper from generative AI?

A: Only if you verify they are real & relevant. Submitting a paper with hallucinated references would violate the ACM Policy on Authorship, and your paper will likely be desk rejected.

Slide from Hot Chips 2025: "2025 TCMM Open Source Hardware Contribution Award: Claire Wolf: In recognition of outstanding contributions to RISC-V — including BitManip, RVFI, and PicoRV32—and to open-source tools like Yosys and IceStorm. [IEEE Computer Society TCMM / Technical Community on Microprocessors and Microcomputers]"

Congratulations @clairexen.bsky.social: #HotChips / IEEE TCMM 2025 Open Source Hardware Contribution Award

@sigplan-pldi.bsky.social was an absolute blast this year and had a lot of interesting conversations and papers! I've written down a little retrospective reflecting on some of them: people.csail.mit.edu/rachit/post/...

At PLDI this year, I received the SIGPLAN John C. Reynolds Distinguished Dissertation award and at ISCA, I received an honorable mention for the SIGARCH / TCCA Outstanding dissertation award!

Truly honored to receive recognition from both the communities! Really excited for what comes next!

somehow in $CURRENT_YEAR, I still can't get OCaml's LSP to jump to the correct definition for me after hours of debugging....

PLMW @ PLDI 2025 - Programming Languages Mentoring Workshop - PLDI 2025 The Programming Language Mentoring Workshop (PLMW) aims to broaden the exposure of late-stage undergraduate students and early-stage graduate students to research and career opportunities in programmi...

PLMW@PLDI'25 is now accepting applications: pldi25.sigplan.org/home/PLMW-pl...

Deadline: April 10, 2025

PLMW an excellent place to learn about exciting PL research, from the ground up, and to find your PL friends!

Please apply!

implicit public modules baaaaad

one of us! one of us!

SPAA'25 is seeking submissions! Uniquely this year, SPAA seeks a broader set of research areas, including algorithms, systems, PL, applications, quantum, and more. The central theme is parallelism and concurrency.

Deadline: Feb 28

Please consider submitting!

spaa.acm.org/call-for-pap...

Well-deserved! Iris is also a really great example of how well-engineered artifacts make it dramatically easier to pursue technically deep research.

What are people's favorite "core systems" textbooks (OS, Networking, Databases, etc.)?

Which specific idea? I can think of quite a few bits of things that react has that come from academia.

see ur/web, state monad, a long line of @shriram.bsky.social's work