Tavian Barnes

Screenshot of text: Frequently Asked Questions Can I book my flight through an agency or travel agent? Flair Airlines does not sell tickets through agents or third-party websites. Always book at flyflair.com. We do (statement above is false), through google flights and expedia and others, we should clarify here that the thing that you should verify it's a trusted agency

Screenshot: please type "confirm" to proceed confirm this is an invalid value confirm cancellation (disabled button), cancel

Flair Airlines, the budget airline with the even more budget website

... ask HISTORIANS???

New (short) blog post: sneaky git commits

tavianator.com/2025/sneaky....

Nah man rent used to actually be lower

imo the third post is better: tavianator.com/2022/ray_box...

A brief history and (ab)use of __VA_OPT__: tavianator.com/2025/cpp_chu...

38 seconds total, if you read the whole line.

Anyway I'm not suggesting that an "actual project" spend time on this, but maybe a build system should?

New blog post: parallel ./configure

tavianator.com/2025/configu...

Still no sound from my laptop speakers, but at least I won't trigger a UAF anymore while I try to debug it: lore.kernel.org/linux-sound/...

Keep going? No, fail fast!

I could reproduce the phenomenon with only 14 instructions on #Intel #GoldenCove, #RaptorCove, #RedwoodCove. It appears only with the 64b-immediate initialization of the 2nd (3rd) operand in the -1024<=imm32<=1023 range.

On #LionCove... 1/2

And the explanation: tavianator.com/2025/shlxpla...

New blog post: tavianator.com/2025/shlx.html

Re-measured it: the prefetch is still a significant improvement, ~11% higher throughput at 8 threads, ~30% higher at 12 threads. I should probably write this up somewhere

In both cases the counters claim 1 uop, so I don't think so

It's fast for me in practice on Zen 2 at least. Maybe someday I'll microbenchmark it. But also I've dramatically optimized the MPMC queue recently, not sure the prefetch still makes a difference

uops.info Alder Lake-P latency for SHLX · Issue #33 · andreas-abel/nanoBench https://uops.info/html-instr/SHLX_R64_R64_R64.html#ADL-P lists SHLX as having 3-cycle latency for both operands. This is in contrast to Intel's docs and InstLatx64's measurements. So what gives? I ...

I wrote more details here: github.com/andreas-abel...

uops.info Alder Lake-P latency for SHLX · Issue #33 · andreas-abel/nanoBench https://uops.info/html-instr/SHLX_R64_R64_R64.html#ADL-P lists SHLX as having 3-cycle latency for both operands. This is in contrast to Intel's docs and InstLatx64's measurements. So what gives? I ...

I wrote more details here: github.com/andreas-abel...

Okay new discovery: "MOV R10D, 1" also gives 1c latency. But "MOV R10, 1" gives 3c latency. Something to do with whether the top half of the count register is zeroed and how.

Compiler flags of GCC/CLANG to generate "BEXTR" instruction (of IA32's BMI1) I am looking for compiler flags of GCC/CLANG to generate BEXTR instruction. template &lt;auto uSTART, auto uLENGTH, typename Tunsigned&gt; constexpr Tunsigned bit_extract(Tunsigned uInput) { re...

Oh I found this: stackoverflow.com/a/77705726/5...

Maybe a register renaming issue?

So I suspect some code alignment issue or something is at fault

Hmm, something very strange is going on. I can reproduce their benchmark. But if I add "XOR R8, R8; XOR R9, R9; XOR R10, R10" to -asm_init to zero all the registers, it goes from 8 cycles to 6, i.e. 1-cycle latency.

*But*, if I instead use "MOV R10, 0" to zero it out, it's back to 8 cycles!

mac-arm64: Cope with signal handling quirks · chromium/crashpad@e0d8a0a On x86_64, it’s impossible for a signal handler distinguish between SIGBUS caused synchronously by a hardware fault and SIGBUS raised asynchronously by software. This remains true on arm64, and is ...

Crashpad knows about this but otherwise it doesn't seem documented: github.com/chromium/cra...

So it turns out that on arm64 macOS, if you send SIGSEGV manually (kill -SEGV <pid>), the kernel fills in siginfo->si_code as if it were a "real" SIGSEGV. So your handler can't easily distinguish between a "real" and a "fake" SIGSEGV

(Claude output) I'm familiar with tavianator (Brandon Andersen) as a software developer and technical writer who has made contributions to computer graphics, programming optimization, and software development tools. They are known for their blog posts and technical writing about computer science topics, particularly articles about bit manipulation techniques and computational geometry. However, I try to be careful about making specific claims about individuals since I may make mistakes, so I'd encourage you to verify any particular details I've mentioned.

TIL my name

crates.io: Rust Package Registry

Recently I came across the Rust crate signal-hook: crates.io/crates/signa...

What's remarkable is both the API and the implementation are *very* similar, despite having not seen this crate when I wrote my C implementation. Pretty cool that we converged on a similar solution.

A while ago I implemented some code for dynamic signal handler (un)registration: github.com/tavianator/b...

The idea is you can call sighook(SIGINT, ...) from multiple places and all the registered hooks will get called when a signal is received.

Sure! But also go like my posts about cache prefetching or whatever

Experimentally, this is a big benefit (33% fewer stalled cycles), but I'd like to understand the tradeoff better